In memory, a sense amplifier is one of the elements which make up the circuitry on a semiconductor memory chip. The sense amplifier is part of a read circuitry that is used when data is read from the memory. The sense amplifier senses low power signals from a bitline that represents a data bit (1 or 0) stored in a memory cell, and amplifies a small voltage swing to recognizable logic levels so that the data can be interpreted properly by logic outside of the memory.
In a static random-access memory (SRAM) operation, in order to read a bit from a particular memory cell a wordline along the particular memory cell's row is turned on, which activates all of the cells in a row. The stored value (0 or 1) from the particular memory cell is then sent to the bitlines associated with the particular memory cell. The sense amplifier at the end of two complimentary bitlines amplifies the small voltages to a normal logic level. The bit from the desired cell is then latched from the particular memory cell's sense amplifier into a buffer, and placed on an output bus.
In a dynamic random-access memory (DRAM) operation, the sense amplifier operation is similar to the SRAM, but performs an additional function. Specifically, the data in DRAM chips is stored as electric charge in tiny capacitors in memory cells. The read operation depletes the charge in a cell, destroying the data, so after the data is read out the sense amplifier must immediately write it back in the cell by applying a voltage to it (i.e., memory refresh).
In a sense amplifier and a latching scheme, only one output of the sense amplifier is used to actively drive a latch. The other output of the sense amplifier stays precharged and remains unutilized (i.e., not used to drive the latch). The latch in the conventional design is generally a SR NOR latch. In this arrangement, the performance is slowed by a large number of complex stacked gates.
In another type of sense amplifier and latching scheme, a stacked inverter latch is used instead of a SR NOR latch. This reduces the number of complex stacked gates, improving performance. However, in this type of design, there is still only one output of the sense amplifier which is used to actively drive the latch; the other output of the sense amplifier stays precharged and remains unutilized (i.e., not used to drive the latch).